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a
3 V/5 V, 10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC AD7707
FUNCTIONAL BLOCK DIAGRAM
DVDD AVDD REF IN(-) REF IN(+)
FEATURES Charge Balancing ADC 16 Bits No Missing Codes 0.003% Nonlinearity High Level ( 10 V) and Low Level ( 10 mV) Input Channels True Bipolar 100 mV Capability on Low Level Input Channels Without Requiring Charge Pumps Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPITM, QSPITM, MICROWIRETM and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input 2.7 V to 3.3 V or 4.75 V to 5.25 V Operation Power Dissipation 1 mW max @ 3 V Standby Current 8 A max 20-Lead SOIC and TSSOP Packages GENERAL DESCRIPTION
AD7707
AIN1 AIN2 LOCOM 30k AIN3 VBIAS 5k 5k 15k HICOM MCLK IN MCLK OUT 30k CLOCK GENERATION SERIAL INTERFACE REGISTER BANK SCLK CS DIN DOUT A = 1 128 MUX BUF PGA CHARGE BALANCING A/D CONVERTER - MODULATOR DIGITAL FILTER
AGND
DGND
DRDY
RESET
The AD7707 is a complete analog front end for low frequency measurement applications. This three-channel device can accept either low level input signals directly from a transducer or high level ( 10 V) signals and produce a serial digital output. It employs a sigma-delta conversion technique to realize up to 16 bits of no missing codes performance. The selected input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via an on-chip control register allowing adjustment of the filter cutoff and output update rate. The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply. The AD7707 features two low level pseudodifferential analog input channels, one high level input channel and a differential reference input. Input signal ranges of 0 mV to +20 mV through 0 V to +2.5 V can be accommodated on both low level input channels when operating with a VDD of 5 V and a reference of 2.5 V. They can also handle bipolar input signal ranges of 20 mV through 2.5 V, which are referenced to the LCOM input. The AD7707, with a 3 V supply and a 1.225 V reference, can handle unipolar input signal ranges of 0 mV to +10 mV through 0 V to +1.225 V. Its bipolar input signal ranges are 10 mV through 1.225 V. The high level input channel can accept input signal ranges of 10 V, 5 V, 0 V to +10 V and 0 V to +5 V. The AD7707 thus performs all signal conditioning and conversion for a threechannel system.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
The AD7707 is ideal for use in smart, microcontroller or DSPbased systems. It features a serial interface that can be configured for three-wire operation. Gain settings, signal polarity and update rate selection can be configured in software using the input serial port. The part contains self-calibration and system calibration options to eliminate gain and offset errors on the part itself or in the system. CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to 20 W typ. These parts are available in a 20-lead wide body (0.3 inch) small outline (SOIC) package and a low profile 20-lead TSSOP.
PRODUCT HIGHLIGHTS
1. The AD7707 consumes less than 1 mW at 3 V supplies and 1 MHz master clock, making it ideal for use in low power systems. Standby current is less than 8 A. 2. On-chip thin-film resistors allow 10 V, 5 V, 0 V to +10 V and 0 V to +5 V high level input signals to be directly accommodated on the analog inputs without requiring split supplies or charge-pumps. 3. The low level input channels allow the AD7707 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning. 4. The part features excellent static performance specifications with 16 bits, no missing codes, 0.003% accuracy and low rms noise. Endpoint errors and the effects of temperature drift are eliminated by on-chip calibration options, which remove zero-scale and full-scale errors.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
DV = or V, REF with AV = 3 V V with AV = = REFIN(+); MCLK unless AD7707-SPECIFICATIONS (AV5 V;=REF IN(-)+3 VGND;5VBIAS =IN(+) = +1.225 VIN = 2.4576 MHzand +2.5otherwise noted. All specifications T to T unless otherwise noted.)
DD DD DD MIN MAX
DD
Parameter STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes Output Noise Integral Nonlinearity2 Unipolar Offset Error Unipolar Offset Drift4 Bipolar Zero Error Bipolar Zero Drift4 Positive Full-Scale Error5 Full-Scale Drift4, 6 Gain Error7 Gain Drift4, 8 Bipolar Negative Full-Scale Error2 Bipolar Negative Full-Scale Drift4 HIGH LEVEL INPUT CHANNEL (AIN3) No Missing Codes Output Noise Integral Nonlinearity2 Unipolar Offset Error9 Unipolar Offset Drift Bipolar Zero Error9 Bipolar Zero Drift Gain Error Gain Drift Negative Full-Scale Error2
B Version1
Units
Conditions/Comments
16 See Tables I and III 0.003 See Note 3 0.5 See Note 3 0.5 0.1 See Note 3 0.5 See Note 3 0.5 0.003 1 0.6 16 See Tables IV and VI 0.003 10 4 10 4 1 0.2 0.5 0.0012
Bits min % of FSR max V/C typ V/C typ V/C typ V/C typ ppm of FSR/C typ % of FSR max V/C typ V/C typ Bits min % of FSR max mV max V/C typ mV max V/C typ V/C typ % typ ppm of FSR/C typ % of FSR typ
Guaranteed by Design. Filter Notch < 60 Hz Depends on Filter Cutoffs and Selected Gain Filter Notch < 60 Hz. Typically 0.0003%
For Gains 1, 2 and 4 For Gains 8, 16, 32, 64 and 128
Typically 0.0007% For Gains of 1 to 4 For Gains of 8 to 128 Guaranteed by Design. Filter Notch < 60 Hz Depends on Filter Cutoffs and Selected Gain Filter Notch < 60 Hz. Typically 0.0003% Typically Within 1.5 mV Typically Within 1.5 mV For Gains 1, 2 and 4 For Gains 8, 16, 32, 64 and 128 Typically Within 0.05%
LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Input Common-Mode Rejection (CMR)2 AVDD = 5 V Gain = 1 100 Gain = 2 105 Gain = 4 110 Gain = 8 to 128 130 AVDD = 3 V Gain = 1 105 Gain = 2 110 Gain = 4 120 Gain = 8 to 128 130 98 Normal-Mode 50 Hz Rejection2 Normal-Mode 60 Hz Rejection2 98 Common-Mode 50 Hz Rejection2 150 Common-Mode 60 Hz Rejection2 150 Absolute/Common-Mode REF IN Voltage2 AGND to AVDD AGND - 100 mV Absolute/Common-Mode AIN Voltage2, 10 AVDD + 30 mV AGND + 50 mV AVDD - 1.5 V AIN DC Input Current2 1 AIN Sampling Capacitance2 10 AIN Differential Voltage Range11 0 to +VREF/GAIN12 VREF/GAIN AIN Input Sampling Rate, fS GAIN x fCLKIN/64 fCLKIN/8 Reference Input Range REF IN(+) - REF IN(-) Voltage 1/1.75 REF IN(+) - REF IN(-) Voltage REF IN Input Sampling Rate, fS 100 mV INPUT RANGE INL2 Input Common-Mode Rejection (CMR)2 Power Supply Rejection (PSR)2 0.003 80 90 1/3.5 fCLKIN/64
Specifications for AIN and REF IN Unless Noted Low Level Input Channels, AIN1 and AIN2 dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ V min to V max V min V max V min V max nA max pF max nom nom
For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 x fNOTCH For Filter Notches of 10 Hz, 20 Hz, 60 Hz, 0.02 x fNOTCH For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 x fNOTCH For Filter Notches of 10 Hz, 20 Hz, 60 Hz, 0.02 x fNOTCH BUF Bit of Setup Register = 0 BUF Bit of Setup Register = 1
BUF = 0 Unipolar Input Range (B/U Bit of Setup Register = 1) Bipolar Input Range (B/U Bit of Setup Register = 0) For Gains of 1 to 4 For Gains of 8 to 128 AVDD = 2.7 V to 3.3 V. VREF = 1.225 V 1% for Specified Performance AVDD = 4.75 V to 5.25 V. VREF = 2.5 V 1% for Specified Performance Low Level Input Channels, (AIN1 and AIN2) Gain = 16, Unbuffered Mode Filter Notch < 60 Hz
V min/max V min/max
% of FSR max dB typ dB typ
-2-
REV. A
AD7707
Parameter B Version
1
Units V max V min dB typ dB typ
Conditions/Comments AIN3 is with respect to HICOM. For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 x fNOTCH For Filter Notches of 10 Hz, 20 Hz, 60 Hz, 0.02 x fNOTCH For Gains of 1 to 4 For Gains of 8 to 128 Typically 30 k 10%; Typical Resistor Tempco is -30 ppm/C Typically = REFIN(+) = 2.5 V
HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 Voltage Range +10 -10 Normal Mode 50 Hz Rejection 78 Normal Mode 60 Hz Rejection 78 AIN3 Input Sampling Rate, fS GAIN x fCLKIN/64 fCLKIN/8 AIN3 Input Impedance2 27 10 AIN3 Sampling Capacitance2 VBIAS Input Range 0 V/AVDD LOGIC INPUTS Input Current All Inputs Except MCLK IN MCLK All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) VT+ VT- VT+ - VT- SCLK Only (Schmitt Triggered Input) VT+ VT- VT+ - VT- MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance14 Data Output Coding SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16 Input Span16 High Level Input Channels (AIN3) Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16 Input Span16 POWER REQUIREMENTS Power Supply Voltages AVDD Voltage DVDD Voltage Power Supply Currents AVDD Current
k min pF max V min/max
1 10 0.8 0.4 2.0 1.4/3 0.8/1.4 0.4/0.8 1/2.5 0.4/1.1 0.375/0.8 0.8 3.5 0.4 2.5 0.4 0.4 4 DVDD - 0.6 10 9 Binary Offset Binary
A max A max V max V max V min V min/V max V min/V max V min/V max
Typically 20 nA Typically 2 A DVDD = 5 V DVDD = 3 V DVDD = 3 V and 5 V DVDD = 5 V Nominal
DVDD = 3 V Nominal V min/V max V min/V max V min/V max DVDD = 5 V Nominal V max V min DVDD = 3 V Nominal V max V min V max V max V min V min A max pF typ ISINK = 800 A Except for MCLK OUT.13 DVDD = 5 V ISINK = 100 A Except for MCLK OUT.13 DVDD = 3 V ISOURCE = 200 A Except for MCLK OUT.13 DVDD = 5 V ISOURCE = 100 A Except for MCLK OUT.13 DVDD = 3 V
Unipolar Mode Bipolar Mode
(1.05 x VREF)/GAIN - (1.05 x VREF)/GAIN - (1.05 x VREF)/GAIN (0.8 x VREF)/GAIN (2.1 x VREF)/GAIN (8.4 x VREF)/GAIN - (8.4 x VREF)/GAIN - (8.4 x VREF)/GAIN (6.4 x VREF)/GAIN (16.8 x VREF)/GAIN
V max V max V max V min V max V max V max V max V min V max
GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128) GAIN Is The Selected PGA Gain (1 to 128)
+2.7 to +3.3 or +4.75 to +5.25 +2.7 to +5.25
V V
For Specified Performance For Specified Performance AVDD = 3 V or 5 V. Gain = 1 to 4 Typically 0.22 mA. BUF = 0. fCLK IN = 1 MHz or 2.4576 MHz Typically 0.45 mA. BUF = 1. fCLK IN = 1 MHz or 2.4576 MHz AVDD = 3 V or 5 V. Gain = 8 to 128 Typically 0.38 mA. BUF = 0. fCLK IN = 2.4576 MHz Typically 0.81 mA. BUF = 1. fCLK IN = 2.4576 MHz
0.27 0.6
mA max mA max
0.5 1.1
mA max mA max
REV. A
-3-
AD7707-SPECIFICATIONS
Parameter POWER REQUIREMENTS (Continued) DVDD Current17 0.080 0.15 0.18 0.35 See Note 20 mA max mA max mA max mA max dB typ B Version1 Units Conditions/Comments Digital I/Ps = 0 V or DVDD. External MCLK IN Typically 0.06 mA. DVDD = 3 V. fCLK IN = 1 MHz Typically 0.13 mA. DVDD = 5 V. fCLK IN = 1 MHz Typically 0.15 mA. DVDD = 3 V. fCLK IN = 2.4576 MHz Typically 0.3 mA. DVDD = 5 V. fCLK IN = 2.4576 MHz AVDD = DVDD = +3 V. Digital I/Ps = 0 V or DVDD. External MCLK IN Excluding Dissipation in the AIN3 Attenuator Typically 0.84 mW. BUF = 0. fCLK IN = 1 MHz, All Gains. Typically 1.53 mW. BUF = 1. fCLK IN = 1 MHz, All Gains. Typically 1.11 mW. BUF = 0. fCLK IN = 2.4576 MHz, Gain = 1 to 4. Typically 1.9 mW. BUF = 1. fCLK IN = 2.4576 MHz, Gain = 1 to 4. AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD. External MCLKIN Typically 1.75 mW. BUF = 0. fCLK IN = 1 MHz, All Gains. Typically 2.9 mW. BUF = 1. fCLK IN = 1 MHz, All Gains. Typically 2.6 mW. BUF = 0. fCLK IN = 2.4576 MHz. Typically 3.75 mW. BUF = 1. fCLK IN = 2.4576 MHz. External MCLK IN = 0 V or DVDD. Typically 9 A. AVDD = +5 V External MCLK IN = 0 V or DVDD. Typically 4 A. AVDD = +3 V
Power Supply Rejection 19 Normal Mode Power Dissipation17
1.05 2.04 1.35 2.34 Normal Mode Power Dissipation17 2.1 3.75 3.1 4.75 18 8
NOTES
mW max mW max mW max mW max
Standby (Power-Down) Current18
mW max mW max mW max mW max A max A max
Temperature range as follows: B Version, -40C to +85C. These numbers are established from characterization or design at initial product release. 3 A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III for the low level input channels AIN1 and AIN2. This applies after calibration at the temperature of interest. 4 Recalibration at any temperature will remove these drift errors. 5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 7 Gain error does not include zero-scale errors. It is calculated as full-scale error-unipolar offset error for unipolar ranges and full-scale error-bipolar zero error for bipolar ranges. 8 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed. 9 Error is removed following a system calibration. 10 This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative than AGND - 100 mV. Parts are functional with voltages down to AGND - 200 mV, but with increased leakage at high temperature. 11 The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with respect to the HCOM input on the high level input channel AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD + 100 mV, or go more negative than GND - 100 mV for specified performance. Input voltages of AGND - 200 mV can be accommodated, but with increased leakage at high temperature. 12 VREF = REF IN(+) - REF IN(-). 13 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 14 Sample tested at +25C to ensure compliance. 15 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 16 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND - 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 17 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section). 18 If the external master clock continues to run in standby mode, the standby current increases to 150 A typical at 5 V and 75 A at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see Standby Mode section). 19 Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 20 Hz or 60 Hz. 20 PSRR depends on both gain and AVDD.
2
1
Low Level Input Channels, AIN1 and AIN2 Gain AVDD = 3 V AVDD = 5 V 1 86 90 2 78 78 4 85 84 8-128 93 91
High Level Input Channel, AIN3 Gain AVDD = 3 V AVDD = 5 V 1 68 72 2 60 60 4 67 66 8-128 75 73
Specifications subject to change without notice.
-4-
REV. A
AD7707 TIMING CHARACTERISTICS1, 2 Logic = 0, Logic 1 = DV
Parameter fCLKIN
3, 4
(AVDD = DVDD = +2.7 V TO +5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input DD unless otherwise noted.)
Limit at TMIN, TMAX (B Version) 400 5 0.4 x tCLKIN 0.4 x tCLKIN 500 x tCLKIN 100 0 120 0 80 100 100 100 0 10 60 100 100 120 30 20 100 100 0
Units kHz min MHz max ns min ns min ns nom ns min ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max ns max ns max ns min ns min ns min ns min ns min ns min
Conditions/Comments Master Clock Frequency: Crystal Oscillator or Externally Supplied for Specified Performance Master Clock Input Low Time. tCLKIN = 1/fCLKIN Master Clock Input High Time DRDY High Time RESET Pulsewidth DRDY to CS Setup Time CS Falling Edge to SCLK Rising Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD = +5 V DVDD = +3.0 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge to SCLK Rising Edge Hold Time Bus Relinquish Time after SCLK Rising Edge DVDD = +5 V DVDD = +3.0 V SCLK Falling Edge to DRDY High7 CS Falling Edge to SCLK Rising Edge Setup Time Data Valid to SCLK Rising Edge Setup Time Data Valid to SCLK Rising Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge to SCLK Rising Edge Hold Time
tCLKIN LO tCLKIN HI t1 t2 Read Operation t3 t4 t5 5 t6 t7 t8 t9 6 t10 Write Operation t11 t12 t13 t14 t15 t16
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figures 16 and 17. 3 fCLKIN Duty Cycle range is 45% to 55%. f CLKIN must be supplied whenever the AD7707 is not in Standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7707 is production tested with f CLKIN at 2.4576 MHz (1 MHz for some I DD tests). It is guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subsequent reads do not occur close to the next output update.
ISINK (800 A AT VDD = +5V 100 A AT VDD = +3V)
TO OUTPUT PIN 50pF
+1.6V
ISOURCE (200 A AT VDD = +5V 100 A AT VDD = +3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
REV. A
-5-
AD7707
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V AIN1, AIN2 Input Voltage to LOCOM . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V AIN3 Input Voltage to HICOM . . . . . . . . . . . -11 V to +30 V VBIAS to AGND . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V HICOM, LOCOM to AGND . . . . . . -0.3 V to AVDD + 0.3 V REF(+), REF(-) to AGND . . . . . . . . -0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . -0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . -0.3 V to DVDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C
Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 139C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7707BR AD7707BRU EVAL-AD7707EB
VDD Supply 2.7 V to 5.25 V 2.7 V to 5.25 V
Temperature Range -40C to +85C -40C to +85C Evaluation Board
Package Description SOIC TSSOP
Package Options R-20 RU-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7707 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-6-
REV. A
AD7707
PIN CONFIGURATION
SCLK 1 MCLK IN 2 MCLK OUT 3 CS 4 RESET 5 AVDD
6 20 DGND 19 DVDD 18 DIN 17 DOUT
16 DRDY TOP VIEW 15 AGND (Not to Scale) 14 REF IN(-) AIN1 7
AD7707
LOCOM 8 AIN2 9 AIN3 10
13 REF IN(+) 12 VBIAS 11 HICOM
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic SCLK
Function Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in smaller batches of data. Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock frequencies in the range 500 kHz to 5 MHz. When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user does not require it, this MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures that the part is not wasting unnecessary power driving capacitive loads on MCLK OUT. Chip Select. Active low Logic Input used to select the AD7707. With this input hard-wired low, the AD7707 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7707. Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter and analog modulator of the part to power-on status. Analog Supply Voltage, +2.7 V to +5.25 V operation. Low Level Analog Input Channel 1. This is used as a pseudo-differential input with respect to LOCOM. COMMON Input for low level input channels. Analog inputs on AIN1 and AIN2 must be referenced to this input. Low Level Analog Input Channel 2. This is used as a pseudo-differential input with respect to LOCOM. Single-Ended High Level Analog Input Channel with respect to HICOM. COMMON Input for high level input channel. Analog input on AIN3 must be referenced to this input. VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and AIN(-) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected to 2.5 V when AVDD = 5 V and 1.225 V when AVDD = 3 V. Reference Input. Positive input of the differential reference input to the AD7707. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(-). REF IN(+) can lie anywhere between AVDD and AGND.
2
MCLK IN
3
MCLK OUT
4
CS
5 6 7 8 9 10 11 12
RESET AVDD AIN1 LOCOM AIN2 AIN3 HICOM VBIAS
13
REF IN(+)
REV. A
-7-
AD7707
Pin No. 14 Mnemonic REF IN(-) Function Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(-) can lie anywhere between AVDD and AGND provided REF IN(+) is greater than REF IN(-). Analog Ground. Ground reference point for the AD7707's internal analog circuitry. Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data register. The DRDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place between output updates, the DRDY line will return high for 500 x tCLK IN cycles prior to the next output update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from the data register as it is being updated. The DRDY line will return low again when the update has taken place. DRDY is also used to indicate when the AD7707 has completed its on-chip calibration sequence. Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the setup register, communications register, clock register or data register, depending on the register selection bits of the Communications Register. Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the setup register, clock register or communications register, depending, on the register selection bits of the Communications Register. Digital Supply Voltage, +2.7 V to +5.25 V operation. Ground reference point for the AD7707's internal digital circuitry.
15 16
AGND DRDY
17
DOUT
18
DIN
19 20
DVDD DGND
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION)
Table I shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges with a VREF of +2.5 V and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table II shows the rms noise and peak-to-peak resolution when operating in unbuffered mode. It is important to note that the peak-to-peak numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of +2.5 V. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table I. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V AIN1 and AIN2 Unbuffered Mode Only
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.5 Hz 1.2 (16) 3.6 (16) 4.7 (16) 95 (13) 600 (10.5) 1.19 (16) 3.68 (16) 4.78 (16) 100 (13) 543 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution in Bits) Gain of Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 128 0.7 (16) 2.1 (16) 2.6 (16) 65 (13) 316 (10.5) 0.69 (16) 2.18 (16) 2.66 (16) 50.1 (13) 318 (10.5) 0.7 (16) 1.25 (16) 1.5 (16) 23.4 (13) 138 (10.5) 0.71 (16) 1.19 (16) 1.51 (16) 23.5 (13) 132 (10.5) 0.54 (16) 0.89 (16) 0.94 (16) 11.6 (13) 71 (10.5) 0.63 (16) 0.94 (16) 1.07 (16) 11.9 (13) 68.1 (10.5) 0.28 (16) 0.62 (16) 0.73 (16) 6.5 (13) 38 (10.5) 0.27 (16) 0.6 (16) 0.7 (16) 5.83 (13) 33.1 (10.5) 0.28 (16) 0.60 (15.5) 0.68 (15.5) 3.4 (13) 18 (10.5) 0.27 (16) 0.6 (15.5) 0.67 (15.5) 3.64 (13) 17.6 (10.5) 0.28 (15.5) 0.56 (14.5) 0.66 (14.5) 2.1 (12.5) 10 (10) 0.26 (15.5) 0.56 (14.5) 0.66 (14.5) 2.16 (12.5) 9.26 (10.5) 0.27 (14.5) 0.56 (13.5) 0.63 (13.5) 1.5 (12) 5.7 (10) 0.24 (15) 0.56 (13.5) 0.65 (13.5) 1.5 (12) 6.13 (10)
-8-
REV. A
AD7707
Table II. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V AIN1 and AIN2 Buffered Mode Only
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz 1.47 (16) 4.2 (16) 4.9 (16) 104 (13) 572 (10.5) 1.48 (16) 3.9 (16) 5.37 (16) 98.9 (13) 596 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution in Bits) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 0.95 (16) 2.6 (16) 3 (16) 52 (13) 293 (10.5) 8.95 (16) 2.46 (16) 3.05 (16) 52.4 (13) 298 (10.5) 0.88 (16) 1.6 (16) 1.8 (16) 26 (13) 125 (10.5) 0.87 (16) 1.77 (16) 1.89 (16) 26.1 (13) 133 (10.5) 0.55 (16) 1 (16) 1.1 (16) 14 (13) 69 (10.5) 0.67 (16) 1.19 (16) 1.33 (16) 12.7 (13) 69.3 (10.5) 0.42 (16) 0.89 (15.5) 1 (15.5) 6.5 (13) 40 (10.5) 0.41 (16) 0.94 (16) 1.11 (15.5) 6.08 (13) 34.7 (10.5) 0.42 (16) 0.94 (15) 1 (14.5) 4.1 (12.5) 19 (10.5) 0.40 (16) 0.93 (15) 1.06 (14.5) 4.01 (12.5) 16.9 (10.5) 0.42 (15) 0.9 (14) 0.94 (14) 2.7 (12.5) 10 (10.5) 0.40 (15) 0.95 (14) 1.04 (13.5) 2.62 (12.5) 9.67 (10.5)
Gain of 128 0.41 (14) 0.9 (13) 0.94 (13) 2.3 (11.5) 5.9 (10) 0.40 (14) 0.9 (13) 1.02 (12.5) 2.33 (11.5) 6.34 (10)
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION)
Table III shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges with a VREF of +1.225 V and an AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table IV shows the rms noise and peak-to-peak resolution when operating in unbuffered mode. It is important to note that the peak-to-peak numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The numbers given are for bipolar input ranges with a VREF of +1.225 V and for either buffered or unbuffered mode. These numbers are typical and are rounded to the nearest LSB. The numbers apply for the CLK DIV bit of the Clock Register set to 0. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table III. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V AIN1 and AIN2 Unbuffered Mode Only
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz 1.60 (16) 3.8 (16) 4.4 (16) 53 (13) 300 (10.5) 1.56 (16) 3.85 (16) 4.56 (16) 45.7 (13) 262 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution in Bits) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 0.8 (16) 1.9 (16) 2.2 (16) 24 (13) 138 (10.5) 0.88 (16) 2.02 (16) 2.4 (16) 22 (13) 125 (10.5) 0.48 (16) 1.1 (16) 1.35 (16) 15 (13) 80 (10.5) 0.52 (16) 1.15 (16) 1.4 (16) 13.7 (13) 66 (10.5) 0.29 (16) 0.64 (16) 0.78 (16) 6.8 (13) 34 (10.5) 0.3 (16) 0.74 (16) 0.79 (16) 5.27 (13) 32.4 (10.5) 0.29 (16) 0.60 (15.5) 0.7 (15) 3.6 (12.5) 18 (10.5) 0.28 (16) 0.63 (15.5) 0.68 (15) 2.64 (13) 18.4 (10.5) 0.27 (15.5) 0.6 (14.5) 0.68 (14.5) 2.1 (12.5) 8.7 (10.5) 0.27 (15.5) 0.57 (14.5) 0.66 (14.5) 2 (12.5) 8.6 (10.5) 0.26 (14.5) 0.6 (13.5) 0.64 (13.5) 1.5 (12) 4.8 (10) 0.27 (14.5) 0.61 (13.5) 0.64 (13.5) 1.59 (12) 4.64 (10.5)
Gain of 128 0.26 (13.5) 0.6 (12.5) 0.64 (12.5) 1.3 (11) 3.4 (10) 0.26 (13.5) 0.58 (12.5) 0.64 (12.5) 1.4 (11) 3.3 (10)
REV. A
-9-
AD7707
Table IV. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V AIN1 and AIN2 Buffered Mode Only
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz 1.80 (16) 4.1 (16) 5.1 (16) 50 (13) 275 (10.5) 1.75 (16) 4.21 (16) 5.15 (16) 46.1 (13) 282 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution in Bits) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 1 (16) 2.4 (16) 3 (16) 27 (13) 125 (10.5) 1.18 (16) 2.5 (16) 2.8 (16) 24.3 (13) 123 (10.5) 0.7 (16) 1.5 (16) 1.8 (16) 12.3 (13) 80 (10.5) 0.67 (16) 1.48 (16) 1.8 (16) 13.6 (13) 66 (10.5) 0.41 (16) 1 (15.5) 1.1 (15.5) 6.4 (13) 39 (10.5) 0.44 (16) 1 (15.5) 1.15 (15.5) 6.71 (13) 35.3 (10.5) 0.41 (16) 0.91 (15) 0.94 (14.5) 4 (12.5) 16 (10.5) 0.41 (16) 0.94 (15) 1 (14.5) 4.1 (12.5) 14.8 (10.5) 0.41 (15) 0.89 (14) 0.94 (13.5) 2.7 (12.5) 8.9 (10.5) 0.44 (15) 0.96 (14) 1.02 (13.5) 2.54 (12.5) 9.91 (10.5) 0.41 (14) 0.86 (13) 0.99 (13) 2.2 (11.5) 5.2 (10) 0.43 (14) 0.89 (13) 0.96 (13) 2.3 (11.5) 5.48 (10)
Gain of 128 0.41 (13) 0.83 (12) 0.99 (11.5) 1.8 (11) 4.2 (9.5) 0.43 (13) 0.86 (12) 1.03 (11.5) 2.15 (10.5) 4.01 (9.5)
OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION)
Table V shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the 10 V, 5 V, 0 to 5 V and 0 V to +10 V ranges with a VREF of +2.5 V, HBIAS = 2.5 V, HICOM = AGND and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V. Table VI meanwhile shows the output rms noise and peak-to-peak resolution in buffered mode. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. Operating the high level channel with a gain of 2 in bipolar mode gives an operating range of 10 V. Operating at a gain of 2 in unipolar mode gives a range of 0 V to +10 V. Operating the high level channel with a gain of 4 in bipolar mode gives the 5 V operating range. Operating at a gain of 4 in unipolar mode gives an operating range of 0 V to +5 V. Noise for all input ranges is shown in Appendix 1. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table V. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V AIN3 Unbuffered Mode Only
Filter First Notch and O/P Data Rate
10 V Range 5 V Range 0 V to +10 V Range 0 V to +5 V Range -3 dB RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) Frequency ( V) Resolution ( V) Resolution ( V) Resolution ( V) Resolution 5.10 15.82 20.36 430 2350 5.13 18.9 23.7 406 2184 16 16 16 13 10 16 16 16 13 10.5 3.52 9.77 12.29 212 1287 3.53 13.25 15.3 174 1144 16 16 16 13 10 16 16 16 13 10.5 5.10 15.82 20.36 430 2350 5.13 18.9 23.7 406 2184 16 16 16 12 9 16 16 16 12 9.5 3.52 9.77 12.29 212 1287 3.53 13.25 15.3 174 1144 16 16 16 12 9 16 16 15.5 12 9.5
MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz
-10-
REV. A
AD7707
Table VI. Output RMS Noise/ Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V AIN3 Buffered Mode Only Filter First Notch and O/P -3 dB Data Rate Frequency MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz 10 V Range 5 V Range 0 V to +10 V Range 0 to +5 V Range RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) ( V) Resolution ( V) Resolution ( V) Resolution ( V) Resolution 7.4 22.2 26.6 475 2423 7.63 20.25 23.5 377 2226 16 16 16 13 10.5 16 16 16 13 10.5 5.2 14.3 15.85 187 1097 5.45 13.3 14.6 210 1132 16 16 16 13 10.5 16 16 16 13 10.5 7.4 22.2 26.6 475 2423 7.63 20.25 23.5 377 2226 16 16 16 12 9.5 16 16 16 12 9.5 5.2 14.3 15.85 187 1097 5.45 13.3 14.6 210 1132 16 16 16 12 9.5 16 16 15.5 12 9.5
OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION)
Table VII shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the 5 V, 0 V to +5 V and 0 V to +10 V ranges with a VREF of +1.225 V, HBIAS = 1.225 V, HICOM = AGND and AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V for unbuffered mode of operation. The above operating ranges are only achievable in unbuffered mode when operating at 3 V due to common-mode limitations on the input amplifier. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. Operating at a gain of 1 in unipolar mode provides a range of 0 V to +10 V. Operating the high level channel with a gain of 2 in bipolar mode provides a 5 V operating range. Operating at a gain of 2 in unipolar mode provides an operating range of 0 V to +5 V. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table VII. Output RMS Noise/ Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V AIN3 Unbuffered Mode Only
Filter First Notch and O/P Data Rate
-3 dB Frequency
0 V to +10 V Range RMS Noise P-P (Bits) ( V) Resolution 12.4 30.35 34.55 498 2266 13.9 32.2 33.4 430 2207 16 16 16 12.5 10.5 16 16 16 13 10.5
5 V Range RMS Noise P-P (Bits) ( V) Resolution 7.02 16.4 19.13 204 1151 7.3 17.4 18.57 200 1048 16 16 16 13 10.5 16 16 16 13 10.5
0 to +5 V Range RMS Noise P-P (Bits) ( V) Resolution 7.02 16.4 19.13 204 1151 7.3 17.4 18.57 200 1048 16 15.5 15 12 9.5 16 15 15 12 9.5
MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 20 Hz 5.24 Hz 25 Hz 6.55 Hz 100 Hz 26.2 Hz 200 Hz 52.4 Hz
REV. A
-11-
AD7707
32771 32770 32769
CODE READ
VDD = 5V VREF = 2.5V GAIN = 128 50Hz UPDATE RATE
TA = +25 C RMS NOISE = 600nV
400
300 OCCURRENCE
32768 32767 32766 32765 32764 32763 0 100 200 300 400 500 600 READING NO. 700 800 900 1000
200
100
0 32764 32765 32766 32767 CODE 32768 32769 32770
Figure 2. Typical Noise Plot @ Gain = 128 with 50 Hz Update Rate for Low Level Input Channel
Figure 5. Histogram of Data in Figure 2
32769 10Hz UPDATE RATE, UNBUFFERED MODE GAIN = 2, ( 10V INPUT RANGE) BIPOLAR MODE ANALOG INPUT SET ON CODE TRANSITION
800 700 600 10Hz UPDATE RATE UNBUFFERED MODE BIPOLAR MODE GAIN = 2, ( 10V INPUT RANGE)
32768
OCCURRENCE
500 400 300 200 100
CODE
32767 32766 0 200 400 600 READING NO. 800 1000
0 1 32767 CODE 2 32768
Figure 3. Typical Noise Plot for AIN3, High Level Input Channel
Figure 6. Histogram of Data in Figure 3
10 9 8 7
HIGH LEVEL INPUT CHANNEL 10V INPUT RANGE 10Hz UPDATE RATE
0.6
0.5
LOW LEVEL INPUT CHANNEL GAIN = 128 10Hz UPDATE RATE
RMS NOISE - V
RMS NOISE - V
6 5 4 3 2
BUFFERED MODE AVDD = DVDD = 5V REFIN(+) = 2.5V REFIN(-) = AGND TA = +25 C
0.4
BUFFERED MODE
0.3 UNBUFFERED MODE 0.2 AVDD = DVDD = 5V REFIN(+) = 2.5V REFIN(-) = AGND TA = +25 C -15 -10 -5 0 5 INPUT VOLTAGE - mV 10 15 20
UNBUFFERED MODE
0.1
1 0 -10
0 -20
-6
-2 2 AIN3 - Volts
6
10
Figure 4. Typical RMS Noise vs. Analog Input Voltage for High Level Input Channel, AIN3
Figure 7. Typical RMS Noise vs. Analog Input Voltage for Low Level Input Channels, AIN1 and AIN2
-12-
REV. A
AD7707
TEK STOP: SINGLE SEQ 50.0kS/s
20 16
A
VDD 1
MCLK IN = 0V OR VDD 12 VDD = 5V 8 VDD = 3V 4
2 OSCILLATOR = 4.9152 MHz
2 OSCILLATOR = 2.4576 MHz CH1 5.00V CH2 2.00V 5ms/DIV
0 -40 -30 -20 -10 0 10 20 30 40 TEMPERATURE - C 50 60 70 80
Figure 8. Typical Crystal Oscillator Power-Up Time
STANDBY CURRENT -
Figure 9. Standby Current vs. Temperature
ON-CHIP REGISTERS
The AD7707 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a Communications Register that controls the channel selection, decides whether the next operation is a read or write operation and also decides which register the next read or write operation accesses. All communications to the part must start with a write operation to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any other register on the part (including the Communications Register itself and the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The Communications Register also controls the standby mode and channel selection and the DRDY status is also available by reading from the Communications Register. The second register is a Setup Register that determines calibration mode, gain setting, bipolar/unipolar operation and buffered mode. The third register is labelled the Clock Register and contains the filter selection bits and clock control bits. The fourth register is the Data Register from which the output data from the part is accessed. The final registers are the calibration registers which store channel calibration data. The registers are discussed in more detail in the following sections.
Communications Register (RS2, RS1, RS0 = 0, 0, 0)
The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7707 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7707 returns to this default state. Table VIII outlines the bit designations for the Communications Register.
Table VIII. Communications Register
0/DRDY (0)
RS2 (0)
RS1 (0)
RS0 (0)
R/W (0)
STBY (0)
CH1 (0)
CH0 (0)
0/DRDY
For a write operation, a "0" must be written to this bit so that the write operation to the Communications Register actually takes place. If a "1" is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a "0" is written to this bit. Once a "0" is written to this bit, the next seven bits will be loaded to the Communications Register. For a read operation, this bit provides the status of the DRDY flag from the part. The status of this bit is the same as the DRDY output pin. Register Selection Bits. These three bits select to which one of eight on-chip registers the next read or write operation takes place, as shown in Table IX, along with the register size. When the read or write operation to the selected register is complete, the part returns to where it is waiting for a write operation to the Communications Register. It does not remain in a state where it will continue to access the register.
RS2-RS0
REV. A
-13-
AD7707
Table IX. Register Selection
RS2 0 0 0 0 1 1 1 1 R/W
RS1 0 0 1 1 0 0 1 1
RS0 0 1 0 1 0 1 0 1
Register Communications Register Setup Register Clock Register Data Register Test Register No Operation Offset Register Gain Register
Register Size 8 Bits 8 Bits 8 Bits 16 Bits 8 Bits 24 Bits 24 Bits
Read/Write Select. This bit selects whether the next operation is a read or write operation to the selected register. A "0" indicates a write cycle for the next operation to the appropriate register, while a "1" indicates a read operation from the appropriate register. Standby. Writing a "1" to this bit puts the part into its standby or power-down mode. In this mode, the part consumes only 8 A of power supply current. The part retains its calibration coefficients and control word information when in STANDBY. Writing a "0" to this bit places the part in its normal operating mode. The serial interface on the AD7707 remains operational when the part is in STBY mode. Channel Select. These two bits select a channel for conversion or for access to the calibration coefficients as outlined in Table X. Three pairs of calibration registers on the part are used to store the calibration coefficients following a calibration on a channel. They are shown in Tables VII for the AD7707 to indicate which channel combinations have independent calibration coefficients. With CH1 at Logic 1 and CH0 at a Logic 0, the part looks at the LOCOM input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the LOCOM input should be connected to an external voltage within the allowable common-mode range for the part.
Table X. Channel Selection for AD7707
STBY
CH1-CH0
CH1 0 0 1 1
CH0 0 1 0 1
AIN AIN1 AIN2 LOCOM AIN3
Reference LOCOM LOCOM LOCOM HICOM
Calibration Register Pair Register Pair 0 Register Pair 1 Register Pair 0 Register Pair 2
-14-
REV. A
AD7707
Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 01 Hex
The Setup Register is an eight-bit register from which data can either be read or to which data can be written. Table XI outlines the bit designations for the Setup Register.
Table XI. Setup Register
MD1 (0) MD0 (0) G2 (0) G1 (0) G0 (0) B/U (0) BUF (0) FSYNC (1)
MD1 0 0
MD0 0 1
Operating Mode Normal Mode: this is the normal mode of operation of the device whereby the device is performing normal conversions. Self-Calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the Communications Register. This is a one-step calibration sequence and when complete the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the fullscale calibration is performed at the selected gain on an internally-generated VREF/Selected Gain. Zero-Scale System Calibration: this activates zero scale system calibration on the channel selected by CH1 and CH0 of the Communications Register. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. Full-Scale System Calibration: this activates full-scale system calibration on the selected input channel. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. Once again, the DRDY output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. Gain Selection Bits. These bits select the gain setting for the on-chip PGA as outlined in Table XII.
Table XII. Gain Selection
1
0
1
1
G2-G0
G2 0 0 0 0 1 1 1 1 B/U BUF
G1 0 0 1 1 0 0 1 1
G0 0 1 0 1 0 1 0 1
Gain Setting 1 2 4 8 16 32 64 128
Bipolar/Unipolar Operation. A "0" in this bit selects Bipolar Operation. A "1" in this bit selects Unipolar Operation. Buffer Control. With this bit at "0," the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current flowing in the VDD line is reduced. When this bit is high, the on-chip buffer is in series with the analog input allowing the input to handle higher source impedances. Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit goes low, the modulator and filter start to process data and a valid word is available in 3 x 1/ (output update rate), i.e., the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low.
FSYNC
REV. A
-15-
AD7707
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 05 Hex
The Clock Register is an 8-bit register from which data can either be read or to which data can be written. Table XIII outlines the bit designations for the Clock Register.
Table XIII. Clock Register
ZERO (0)
ZERO (0)
CLKDIS (0)
CLKDIV (0)
CLK (1)
FS2 (0)
FS1 (0)
FS0 (1)
ZERO CLKDIS
Zero. A zero MUST be written to these bits to ensure correct operation of the AD7707. Failure to do so may result in unspecified operation of the device. Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock on the MCLK IN pin, the AD7707 continues to have internal clocks and will convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take place when the CLKDIS bit is active. Clock Divider Bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two before being used internally by the AD7707. For example, when this bit is set to 1, the user can operate with a 4.9152 MHz crystal between MCLK IN and MCLK OUT and internally the part will operate with the specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used internally by the part. Clock Bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set to a "1." If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit should be set to a "0." This bit sets up the appropriate scaling currents for a given operating frequency and also chooses (along with FS2, FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the master clock frequency of the device, then the AD7707 may not operate to specification.
CLKDIV
CLK
FS2, FS1, FS0 Filter Selection Bits. Along with the CLK bit, FS2, FS1 and FS0 determine the output update rate, filter first notch and -3 dB frequency as outlined in Table XIV. The on-chip digital filter provides a sinc3 (or Sinx/x3) filter response. Placing the first notch at 10 Hz places notches at both 50 and 60 Hz giving better than 150 dB rejection at these frequencies. In association with the gain selection the filter cutoff also determines the output noise of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I to IV show the effect of filter notch frequency and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a 50 Hz output rate or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when any of these bits are changed. The settling time of the filter to a full-scale step input is worst case 4 x 1/(output data rate). For example, with the filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms max. If the first notch is at 500 Hz, the settling time is 8 ms max. This settling time can be reduced to 3 x 1/ (output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling time will be 3 x 1/(output data rate) from when the FSYNC bit returns low. The -3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter -3 dB frequency = 0.262 x filter first notch frequency
-16-
REV. A
AD7707
Table XIV. Output Update Rates
CLK* 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Output Update Rate 20 Hz 25 Hz 100 Hz 200 Hz 50 Hz 60 Hz 250 Hz 500 Hz 4.054 Hz 4.23 Hz 4.84 Hz 4.96 Hz 10 Hz 10.34 Hz 11.90 Hz 12.2 Hz
-3 dB Filter Cutoff 5.24 Hz 6.55 Hz 26.2 Hz 52.4 Hz 13.1 Hz 15.7 Hz 65.5 Hz 131 Hz 1.06 Hz 1.11 Hz 1.27 Hz 1.3 Hz 2.62 Hz 2.71 Hz 3.13 Hz 3.2 Hz
*Assumes correct clock frequency on MCLK IN pin with CLKDIV bit set appropriately.
Data Register (RS2, RS1, RS0 = 0, 1, 1)
The Data Register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If the Communications Register sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the Communications Register. However, the 16 bits of data written to the part will be ignored by the AD7707.
Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 00 Hex
The part contains a Test Register that is used when testing the device. The user is advised not to change the status of any of the bits in this register from the default (Power-on or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly.
Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 1F4000 Hex
The AD7707 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in conjunction with its associated full-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table VII. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking the FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 5761AB Hex
The AD7707 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written otherwise no data will be transferred to the register. This register is used in conjunction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table X. While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking FSYNC bit in the mode register high before the calibration register operation and taking it low after the operation is complete.
REV. A
-17-
AD7707
CALIBRATION SEQUENCES
The AD7707 contains a number of calibration options as previously outlined. Table XV summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete, but also that the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the Setup Register. When these bits return to 0 (0 following a calibration command), it indicates that the calibration sequence is complete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0 00 represents the duration of the calibration carried out). The sequence to when DRDY goes low also includes a normal conversion and a pipeline delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 x tCLKIN. The time for both methods is given in the table.
Table XV. Calibration Sequences
Calibration Type Self-Calibration ZS System Calibration FS System Calibration
MD1, MD0 0, 1 1, 0 1, 1
Calibration Sequence Internal ZS Cal @ Selected Gain + Internal FS Cal @ Selected Gain ZS Cal on AIN @ Selected Gain FS Cal on AIN @ Selected Gain
Duration to Mode Bits 6 x 1/Output Rate 3 x 1/Output Rate 3 x 1/Output Rate
Duration to DRDY 9 x 1/Output Rate + tP 4 x 1/Output Rate + tP 4 x 1/Output Rate + tP
-18-
REV. A
AD7707
CIRCUIT DESCRIPTION
The AD7707 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. It contains a sigma-delta (or chargebalancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port. The part consumes only 320 A of power supply current, making it ideal for battery-powered or loop-powered instruments. On-chip thin-film resistors allow 10 V, 5 V, 0 V to +10 V and 0 V to +5 V high level input signals to be directly accommodated on the analog input without requiring split supplies, dc-dc converters or charge pumps. This part operates with a supply voltage of 2.7 V to 3.3 V or 4.75 V to 5.25 V. The AD7707 contains two low level (AIN1 and AIN2) programmable-gain pseudo-differential analog input channels and one high level (AIN3) single-ended input channel. For the low level input channels the selectable gains are 1, 2, 4, 8, 16, 32, 64 and 128 allowing the part to accept unipolar signals of between 0 mV to +20 mV and 0 V to +2.5 V, or bipolar signals in the range from 20 mV to 2.5 V when the reference input voltage equals +2.5 V. With a reference voltage of +1.225 V, the input ranges are from 0 mV to +10 mV to 0 V to +1.225 V in unipolar mode, and from 10 mV to 1.225 V in bipolar mode. Note that the signals are with respect to the LOCOM input. The high level input channel can directly accept input signals of 10 V with respect to HICOM when operating with 5 V supplies and a reference of 2.5 V. With 3 V supplies 5 V can be accommodated on the AIN3 input. The input signal to the analog input is continuously sampled at a rate determined by the frequency of the master clock, MCLK IN, and the selected gain. A charge-balancing A/D converter
ANALOG +5V SUPPLY 10 F 0.1 F
(Sigma-Delta Modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. The programmable gain function on the analog input is also incorporated in this sigma-delta modulator with the input sampling frequency being modified to give the higher gains. A sinc3 digital low-pass filter processes the output of the sigmadelta modulator and updates the output register at a rate determined by the first notch frequency of this filter. The output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. The first notch of this digital filter (and hence its -3 dB frequency) can be programmed via the Setup Register bits FS0 and FS1. With a master clock frequency of 2.4576 MHz, the programmable range for this first notch frequency is from 10 Hz to 500 Hz, giving a programmable range for the -3 dB frequency of 2.62 Hz to 131 Hz. With a master clock frequency of 1 MHz, the programmable range for this first notch frequency is from 4 Hz to 200 Hz, giving a programmable range for the -3 dB frequency of 1.06 Hz to 52.4 Hz. The basic connection diagram for the AD7707 is shown in Figure 10. An AD780 or REF192, precision +2.5 V reference, provides the reference source for the part. On the digital side, the part is configured for three-wire operation with CS tied to DGND. A quartz crystal or ceramic resonator provide the master clock source for the part. In most cases, it will be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary, depending on the manufacturer's specifications. A similar circuit is applicable for operation with 3 V supplies, in this case a 1.225 V reference (AD1580) should be used for specified performance.
0.1 F
AVDD LOW LEVEL ANALOG INPUT HIGH LEVEL ANALOG INPUT ANALOG +5V SUPPLY AIN1 AIN2 LOCOM AIN3 VBIAS HICOM
DVDD
AD7707
DRDY DOUT DIN SCLK DATA READY RECEIVE (READ) SERIAL DATA SERIAL CLOCK +5V RESET CS
AGND DGND
VIN VOUT AD780/ REF192 GND 10 F 0.1 F REF IN(-) REF IN(+)
MCLK IN
MCLK OUT
CRYSTAL OR CERAMIC RESONATOR
Figure 10. Basic Connection Diagram for 5 V Operation
REV. A
-19-
AD7707
ANALOG INPUT Analog Input Ranges
The AD7707 contains two low level pseudo-differential analog input channels AIN1 and AIN2. These input pairs provide programmable-gain, differential input channels that can handle either unipolar or pseudo bipolar input signals. It should be noted that the bipolar input signals are referenced to the LOCOM input. The AD7707 also has a high level analog input channel AIN 3 which is referenced to HICOM. Figure 11 shows the input structure on the high level input channel. In normal 5 V operation VBIAS is normally connected to 2.5 V and HICOM is connected to AGND. This arrangement ensures that the voltages seen internally are within the common-mode range of the buffer in buffered mode and within the supply range in unbuffered mode. This device can be programmed to operate in either buffered or unbuffered mode via the BUF bit in the setup register. Note that the signals on AIN3 are with respect to the HICOM input and not with respect to AGND or DGND. The differential voltage seen by the AD7707 when using the high level input channel is the difference between AIN3(+) and AIN3(-) on the mux as shown in Figure 11. AIN3(+) = (AIN3 + 6 x VBIAS+ V (HICOM))/8
6R AIN3 VBIAS 1R 1R = 5k AIN3(+) MUX
CSAMP must be charged through RSW and any additional source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for CSAMP and this may result in gain errors on the part. Table XVI shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Note that these capacitances are total capacitances on the analog input. This external capacitance includes 10 pF from pins and lead frame of the device.
AIN(+)
RSW (7k
TYP)
AIN(-)
CSAMP (7pF) VDD/2
FIRST INTEGRATOR HIGH INPUT IMPEDANCE 1G
SWITCHING FREQUENCY DEPENDS ON fCLKIN AND SELECTED GAIN
Figure 12. Unbuffered Analog Input Structure
Table XVI. External R, C Combination for No 16-Bit Gain Error on Low Level Input Channels (Unbuffered Mode Only) External Capacitance (pF) 50 100 500 1000 90.6 k 44.2 k 21.2 k 9.6 k 54.2 k 26.4 k 12.6 k 5.8 k 14.6 k 7.2 k 3.4 k 1.58 8.2 k 4 k 1.94 k 880
Gain 1 2 4 8-128
0 368 k 177.2 k 82.8 k 35.2 k
400 350
5000 2.2 k 1.12 k 540 240
AIN3(-)
3R HICOM 6R
Figure 11. AIN3 Input Structure
EXTERNAL RESISTANCE - k
AIN3(-) = V (HICOM) + 0.75 x (VBIAS - V (HICOM)) In unbuffered mode, the common-mode range of the low level input channels is from AGND - 100 mV to AVDD + 30 mV. This means that in unbuffered mode the part can handle both unipolar and bipolar input ranges for all gains. Absolute voltages of AGND - 100 mV can be accommodated on the analog inputs without degradation in performance, but leakage current increases appreciably with increasing temperature. In buffered mode, the analog inputs can handle much larger source impedances, but the absolute input voltage range is restricted to between AGND + 50 mV to AVDD - 1.5 V which also places restrictions on the common-mode range. This means that in buffered mode there are some restrictions on the allowable gains for bipolar input ranges. Care must be taken in setting up the common-mode voltage and input voltage range so that the above limits are not exceeded, otherwise there will be a degradation in linearity performance. In unbuffered mode, the analog inputs look directly into the 7 pF input sampling capacitor, CSAMP. The dc input leakage current in this unbuffered mode is 1 nA maximum. As a result, the analog inputs see a dynamic load that is switched at the input sample rate (see Figure 12). This sample rate depends on master clock frequency and selected gain. CSAMP is charged to AIN(+) and discharged to AIN(-) every input sample cycle. The effective on-resistance of the switch, RSW, is typically 7 k.
GAIN = 1 300 250 200 150 100 GAIN = 4 50 0 GAIN = 2
GAIN = 8-128
0
10 100 1000 EXTERNAL CAPACITANCE - pF
10000
Figure 13. External R, C Combination for No 16-Bit Gain Error on Low Level Input Channels (Unbuffered Mode Only)
In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. CSAMP is charged via this buffer amplifier such that source impedances do not affect the charging of CSAMP. This buffer amplifier has an offset leakage current of 1 nA. In buffered mode, large source impedances result in a small dc offset voltage developed across the source impedance, but not in a gain error.
-20-
REV. A
AD7707
Input Sample Rate
The modulator sample frequency for the AD7707 remains at fCLKIN/128 (19.2 kHz @ fCLKIN = 2.4576 MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table XVII). In buffered mode, the input impedance is constant. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/CSAMP x fS where C SAMP is the input sampling capacitance and fS is the input sample rate.
Table XVII. Input Sampling Frequency vs. Gain
Gain 1 2 4 8-128
Input Sampling Frequency (fS) fCLKIN/64 (38.4 kHz @ fCLKIN = 2.4576 MHz) 2 x fCLKIN/64 (76.8 kHz @ fCLKIN =2.4576 MHz) 4 x fCLKIN/64 (76.8 kHz @ fCLKIN =2.4576 MHz) 8 x fCLKIN/64 (307.2 kHz @ fCLKIN = 2.4576 MHz)
The output noise performance outlined in Tables I through IV is for an analog input of 0 V, which effectively removes the effect of noise from the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7707. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7707. In bridge transducer applications where the reference voltage for the ADC is derived from the excitation voltage the effect of the noise in the excitation voltage will be removed as the application is ratiometric. Recommended reference voltage sources for the AD7707 with an AVDD of 5 V include the AD780, REF43 and REF192, while the recommended reference sources for the AD7707 operated with an AVDD of 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references in order to further reduce the noise level.
DIGITAL FILTERING
Bipolar/Unipolar Inputs
The analog inputs on the low level input channels on the AD7707 can accept either unipolar or bipolar input voltage ranges with respect to LOCOM. The high level input channel handles true bipolar signals of 10 V max for guaranteed operation. Bipolar or unipolar options are chosen by programming the B/U bit of the Setup Register. This programs the channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the channel conditions, it simply changes the data output coding and the points on the transfer function where calibrations occur. In unipolar operation the output coding is straight binary. In bipolar mode the output coding is offset binary.
REFERENCE INPUT
The AD7707 contains an on-chip low-pass digital filter which processes the output of the part's sigma-delta modulator. Therefore, the part not only provides the analog-to-digital conversion function but also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7707 has overrange headroom built into the sigma-delta modulator and digital filter, which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). In addition, the digital filter does not provide any rejection at integer multiples of the digital filter's sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter's sampling frequency so that the unattenuated bands actually occur around multiples of the sampling frequency fS (as defined in Table XV). Thus the unattenuated bands occur at n x fS (where n = 1, 2, 3 . . .). At these frequencies, there are frequency bands, f3 dB wide f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output.
The AD7707 reference inputs, REF IN(+) and REF IN(-), provide a differential reference input capability. The commonmode range for these differential inputs is from GND to AVDD. The nominal reference voltage, VREF REF IN(+) - REF IN(-), for specified operation, is +2.5 V for the AD7707 operated with an AVDD of 5 V and +1.225 V for the AD7707 operated with an AVDD of +3 V. The part is functional with VREF voltages down to 1 V, but with degraded performance since the LSB size is smaller. REF IN(+) must always be greater than REF IN(-) for correct operation of the AD7707. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is 1 nA over temperature, and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5 k typ and the reference capacitor (CREF) varies with gain. The sample rate on the reference inputs is fCLKIN/64 and does not vary with gain. For gains of 1 and 2, CREF is 8 pF; for a gain of 16, it is 5.5 pF; for a gain of 32, it is 4.25 pF; for a gain of 64, it is 3.625 pF and for a gain of 128, it is 3.3125 pF.
REV. A
-21-
AD7707
Filter Characteristics
The AD7707's digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for this filter is described in the z-domain by:
H (z ) = 1 N x 1 - Z -N 1 - Z -1
3
and in the frequency domain by: 3 SIN ( N x x f / fS ) 1 H( f ) = x N SIN ( x f / f S ) where N is the ratio of the modulator rate to the output rate. Phase Response:
Since the AD7707 contains this on-chip, low-pass filtering, a settling time is associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a fullscale step input can be up to four times the output data period. For a synchronized step input (using the FSYNC function), the settling time is three times the output data period.
Post-Filtering
H = -3 ( N - 2) x f / fS Rad
Figure 14 shows the filter frequency response for a cutoff frequency of 2.62 Hz, which corresponds to a first filter notch frequency of 10 Hz. The plot is shown from dc to 65 Hz. This response is repeated at either side of the digital filter's sample frequency and at either side of multiples of the filter's sample frequency. The response of the filter is similar to that of an averaging filter, but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter's frequency response. Thus, for the plot of Figure 14 where the output rate is 10 Hz, the first notch of the filter is at 10 Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches.
0 -20 -40 -60 -80
GAIN - dB
The on-chip modulator provides samples at a 19.2 kHz output rate with fCLKIN at 2.4576 MHz. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the programmed output rate of the filter. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. There may, however, be some applications which require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate will require some post-filtering following the digital filter of the AD7707. For example, if the required bandwidth is 7.86 Hz, but the required update rate is 100 Hz, the data can be taken from the AD7707 at the 100 Hz rate giving a -3 dB bandwidth of 26.2 Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz. Post-filtering can also be used to reduce the output noise from the device for bandwidths below 2.62 Hz. At a gain of 128 and a bandwidth of 2.62 Hz, the output rms noise is 450 nV. This is essentially device noise or white noise and since the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 2.62 Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering will result in a longer settling-time.
Analog Filtering
-100 -120 -140 -160 -180 -200 -220 -240 0 10 20 30 40 FREQUENCY - Hz 50 60
Figure 14. Frequency Response of AD7707 Filter
The digital filter does not provide any rejection at integer multiples of the modulator sample frequency, as outlined earlier. However, due to the AD7707's high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7707 are considerably reduced versus a conventional converter with no on-chip filtering. In addition, because the part's common-mode rejection performance of 100 dB extends out to several kHz, common-mode noise in this frequency range will be substantially reduced. Depending on the application, however, it may be necessary to provide attenuation prior to the AD7707 in order to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7707 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7707 in unbuffered mode, care must be taken to ensure that the source impedance is low enough not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing
Simultaneous 50 Hz and 60 Hz rejection is obtained by placing the first notch at 10 Hz. Operating with an update rate of 10 Hz places notches at both 50 Hz and 60 Hz giving better than 100 dB rejection at these frequencies. The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS2 in the CLOCK Register. Programming a different cutoff frequency via FS0 and FS1 does not alter the profile of the filter response, it changes the frequency of the notches. The output update of the part and the frequency of the first notch correspond.
-22-
REV. A
AD7707
filtering which can be provided in front of the AD7707 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 10 k source resistance will cause an offset error of less than 10 V). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7707, it is recommended that the part be operated in buffered mode.
CALIBRATION
to correctly set up the coefficients. If DRDY is low before (or goes low during) the calibration command write to the Setup Register, it may take up to one modulator cycle (MCLK IN/ 128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above but, since the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. Errors due to resistor mismatch in the attenuator on the high level input channel AIN3 are not removed by a self-calibration.
System Calibration
The AD7707 provides a number of calibration options which can be programmed via the MD1 and MD0 bits of the Setup Register. The different calibration options are outlined in the Setup Register and Calibration Sequences sections. A calibration cycle may be initiated at any time by writing to these bits of the Setup Register. Calibration on the AD7707 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. The AD7707 offers self-calibration and system calibration facilities. For full calibration to occur on the selected channel, the onchip microcontroller must record the modulator output for two different input conditions. These are "zero-scale" and "fullscale" points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level that it provides in normal mode. The result of the "zero-scale" calibration conversion is stored in the Zero-Scale Calibration Register while the result of the "full-scale" calibration conversion is stored in the Full-Scale Calibration Register. With these readings, the microcontroller can calculate the offset and the gain slope for the input-to-output transfer function of the converter.
Self-Calibration
System calibration allows the AD7707 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as selfcalibration, but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. Full system calibration requires a two-step process, a ZS System Calibration followed by an FS System Calibration. For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero-scale voltage has been set up, a ZS System Calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the Setup Register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3 x 1/ Output Rate. At this time, the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 x 1/Output Rate as the part performs a normal conversion on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the Setup Register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. After the zero-scale point is calibrated, the full-scale point is applied to AIN and the second step of the calibration process is initiated by again writing the appropriate values (1, 1) to MD1 and MD0. Again, the full-scale voltage must be set up before the calibration is initiated and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3 x 1/Output Rate. At this time, the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 x 1/Output Rate as the part performs a normal conversion
A self-calibration is initiated on the AD7707 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the Setup Register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., AIN1 = LOCOM = Internal Bias Voltage in the case of the AD7707. The PGA is set for the selected gain (as per G1 and G0 bits in the Communications Register) for this zero-scale calibration conversion. The full-scale calibration conversion is performed at the selected gain on an internally-generated voltage of VREF/Selected Gain. The duration time for the calibration is 6 x 1/Output Rate. This is made up of 3 x 1/Output Rate for the zero-scale calibration and 3 x 1/Output Rate for the full-scale calibration. At this time the MD1 and MD0 bits in the Setup Register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 x 1/Output Rate. This is made up of 3 x 1/Output Rate for the zero-scale calibration, 3 x 1/Output Rate for the full-scale calibration, 3 x 1/Output Rate for a conversion on the analog input and some overhead
REV. A
-23-
AD7707
on the AIN voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the Setup Register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the Setup Register in the calibration command. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full-scale. The fact that the system calibration is a two-step calibration offers another feature. After the sequence of a full system calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, will not affect the other parameter. System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage, but the system calibration can be used to remove this error.
Span and Offset Limits on the Low Level Input Channels AIN1 and AIN2
the part is used in unipolar mode and required to remove an offset of 0.2 x VREF/GAIN, the span range the system calibration can handle is 0.85 x VREF/GAIN.
1.05 VREF/GAIN UPPER LIMIT ON AD7707 INPUT VOLTAGE GAIN CALIBRATIONS EXPAND OR CONTRACT THE AD7707 INPUT RANGE -0V DIFFERENTIAL NOMINAL ZERO SCALE POINT
AD7707 LOW LEVEL INPUT CHANNEL INPUT RANGE (0.8 VREF/GAIN TO 2.1 VREF/GAIN)
OFFSET CALIBRATIONS MOVE INPUT RANGE UP OR DOWN LOWER LIMIT ON AD7707 INPUT VOLTAGE -1.05 VREF/GAIN
Figure 15. Span and Offset Limits for Low Level Input Channels AIN1 and AIN2
Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated. The overriding requirement in determining the amount of offset and gain that can be accommodated by the part is the requirement that the positive full-scale calibration limit is < 1.05 x VREF/GAIN. This allows the input range to go 5% above the nominal range. The built-in headroom in the AD7707's analog modulator ensures that the part will still operate correctly with a positive full-scale voltage that is 5% beyond the nominal. The input span in both the unipolar and bipolar modes has a minimum value of 0.8 x VREF/GAIN and a maximum value of 2.1 x VREF/GAIN. However, the span (which is the difference between the bottom of the AD7707's input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. Once again, the offset has to take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative offsets. In both unipolar and bipolar modes, the range of positive offsets that can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05 x VREF/ GAIN. This is best illustrated by looking at a few examples. If the part is used in unipolar mode with a required span of 0.8 x VREF/GAIN, the offset range the system calibration can handle is from -1.05 x VREF/GAIN to +0.25 x VREF/GAIN. If the part is used in unipolar mode with a required span of VREF/ GAIN, the offset range the system calibration can handle is from -1.05 x VREF/GAIN to +0.05 x VREF/GAIN. Similarly, if
If the part is used in bipolar mode with a required span of 0.4 x VREF/GAIN, the offset range the system calibration can handle is from -0.65 x VREF/GAIN to +0.65 x VREF/GAIN. If the part is used in bipolar mode with a required span of VREF/GAIN, then the offset range which the system calibration can handle is from -0.05 x VREF/GAIN to +0.05 x VREF/GAIN. Similarly, if the part is used in bipolar mode and required to remove an offset of 0.2 x VREF/GAIN, the span range the system calibration can handle is 0.85 x VREF/GAIN. Figure 15 shows a graphical representation of the span and offset limits for the low level input channels.
Span and Offset Limits on the High Level Input Channel AIN3
The exact same reasoning as above can be applied to the high level input channel. When using the high level channel the attenuator provides an attenuation factor of 8. All span and offset limits should be multiplied by a factor of 8. Therefore, the range of input span in both the unipolar and bipolar modes has a minimum value of 6.4 x VREF/GAIN and a maximum value of 16.8 x VREF/GAIN. The offset range plus the span range cannot exceed 8.4 x VREF/GAIN.
Power-Up and Calibration
On power-up, the AD7707 performs an internal reset that sets the contents of the internal registers to a known state. There are default values loaded to all registers after power-on or reset. The default values contain nominal calibration coefficients for the calibration registers. However, to ensure correct calibration for the device, a calibration routine should be performed after power-up. A calibration should be performed if the update-rate or gain are changed. The power dissipation and temperature drift of the AD7707 are low and no warm-up time is required before the initial calibration is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. Similarly, if the clock source for the part is generated from a crystal or resonator across the MCLK pins, the start-up time for the oscillator circuit should elapse before a calibration is initiated on the part (see the following).
-24-
REV. A
AD7707
C1 MCLK IN CRYSTAL OR CERAMIC RESONATOR
AD7707
MCLK OUT
C2
Figure 16. Crystal/Resonator Connection for the AD7707
USING THE AD7707 Clocking and Oscillator Circuit
the current drain varies across crystal types. When using a crystal with an ESR of 700 or when using a ceramic resonator, the increase in the typical current over an externally-applied clock is 20 A with DVDD = +3 V and 200 A with DVDD = +5 V. When using a crystal with an ESR of 3 k, the increase in the typical current over an externally applied clock is again 100 A with DVDD = +3 V but 400 A with DVDD = +5 V. The on-chip oscillator circuit also has a start-up time associated with it before it is oscillating at its correct frequency and correct voltage levels. Typical start-up times with DVDD = 5 V are 6 ms using a 4.9512 MHz crystal, 16 ms with a 2.4576 MHz crystal and 20 ms with a 1 MHz crystal oscillator. Start-up times are typically 20% slower when the power supply voltage is reduced to 3 V. At 3 V supplies, depending on the loading capacitances on the MCLK pins, a 1 M feedback resistor may be required across the crystal or resonator in order to keep the start-up times around the 20 ms duration. The AD7707's master clock appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the AD7707's clock, it may be desirable to use this clock as the clock source for the system. In this case, it is recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit.
System Synchronization
The AD7707 requires a master clock input, which may be an external CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK IN and MCLK OUT as shown in Figure 16, in which case the clock circuit will function as an oscillator, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the -3 dB frequency, output update rate and calibration time are all directly related to the master clock frequency, fCLKIN. Reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and double the calibration time. The current drawn from the DVDD power supply is also related to fCLKIN. Reducing fCLKIN by a factor of 2 will halve the DVDD current but will not affect the current drawn from the AVDD. Using the part with a crystal or ceramic resonator between the MCLK IN and MCLK OUT pins generally causes more current to be drawn from DVDD than when the part is clocked from a driven clock signal at the MCLK IN pin. This is because the on-chip oscillator circuit is active in the case of the crystal or ceramic resonator. Therefore, the lowest possible current on the AD7707 is achieved with an externally applied clock at the MCLK IN pin with MCLK OUT unconnected, unloaded and disabled. The amount of additional current taken by the oscillator depends on a number of factors--first, the larger the value of capacitor (C1 and C2) placed on the MCLK IN and MCLK OUT pins, the larger the current consumption on the AD7707. Care should be taken not to exceed the capacitor values recommended by the crystal and ceramic resonator manufacturers to avoid consuming unnecessary current. Typical values for C1 and C2 are recommended by crystal or ceramic resonator manufacturers, these are in the range of 30 pF to 50 pF and if the capacitor values on MCLK IN and MCLK OUT are kept in this range they will not result in any excessive current. Another factor that influences the current is the effective series resistance (ESR) of the crystal that appears between the MCLK IN and MCLK OUT pins of the AD7707. As a general rule, the lower the ESR value the lower the current taken by the oscillator circuit. When operating with a clock frequency of 2.4576 MHz, there is 50 A difference in the current between an externally applied clock and a crystal resonator when operating with a DVDD of +3 V. With DVDD = +5 V and fCLKIN = 2.4576 MHz, the typical current increases by 250 A for a crystal/resonator supplied clock versus an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and as a result there tends to be little difference between different crystal and resonator types. When operating with a clock frequency of 1 MHz, the ESR value for different crystal types varies significantly. As a result, REV. A
The FSYNC bit of the Setup Register allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, i.e., when the FSYNC is changed from 1 to 0. With a 1 in the FSYNC bit of the Setup Register, the digital filter and analog modulator are held in a known reset state and the part is not processing any input samples. When a 0 is then written to the FSYNC bit, the modulator and filter are taken out of this reset state and the part starts to gather samples again on the next master clock edge. The FSYNC input can also be used as a software start convert command allowing the AD7707 to be operated in a conventional converter fashion. In this mode, writing to the FSYNC bit starts conversion and the falling edge of DRDY indicates when conversion is complete. The disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. This means that the rate at which the data register is updated is three times slower in this mode. Since the FSYNC bit resets the digital filter, the full settling time of 3 x 1/Output Rate has to elapse before there is a new word loaded to the output register on the part. If the DRDY signal is low when FSYNC goes to a 0, the DRDY signal will not be reset high by the FSYNC command. This is because the AD7707 recognizes that there is a word in the data register which has not been read. The DRDY line will stay low until an update of the data register takes place, at which time it will go high for 500 x tCLKIN before returning low again. A read from the data register resets the DRDY signal high and it will not return low until the settling time of the filter has elapsed (from the FSYNC command) and there is a valid new word in the data register. If the DRDY line is high when the FSYNC command is issued, the DRDY line will not return low until the settling time of the filter has elapsed.
-25-
AD7707
Reset Input Accuracy
The RESET input on the AD7707 resets all the logic, the digital filter and the analog modulator, while all on-chip registers are reset to their default state. DRDY is driven high and the AD7707 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7707 starts to process data and DRDY will return low in 3 x 1/Output Rate indicating a valid new word in the data register. However, the AD7707 operates with its default setup conditions after a RESET and it is generally necessary to set up all registers and carry out a calibration after a RESET command. The AD7707's on-chip oscillator circuit continues to function even when the RESET input is low. The master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7707's clock, the AD7707 produces an uninterrupted master clock during RESET commands.
Standby Mode
Sigma-Delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7707 achieves excellent linearity by the use of high quality, on-chip capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7707 uses digital calibration techniques that minimize offset and gain error.
Drift Considerations
Charge injection in the analog switches and dc leakage currents at the sampling modes are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain. Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes.
POWER SUPPLIES
The STBY bit in the Communications Register of the AD7707 allows the user to place the part in a power-down mode when it is not required to provide conversion results. The AD7707 retains the contents of all its on-chip registers (including the data register) while in standby mode. When released from standby mode, the part starts to process data and a new word is available in the data register in 3 x 1/Output rate from when a 0 is written to the STBY bit. The STBY bit does not affect the digital interface, nor does it affect the status of the DRDY line. If DRDY is high when the STBY bit is brought low, it will remain high until there is a valid new word in the data register. If DRDY is low when the STBY bit is brought low, it will remain low until the data register is updated, at which time the DRDY line will return high for 500 x tCLKIN before returning low again. If DRDY is low when the part enters its standby mode (indicating a valid unread word in the data register), the data register can be read while the part is in standby. At the end of this read operation, the DRDY will be reset high as normal. Placing the part in standby mode reduces the total current to 9 A typical with 5 V supplies and 4 A with 3 V supplies when the part is operated from an external master clock provided this master clock is stopped. If the external clock continues to drive the MCLK IN pin in standby mode, the standby current increases to 150 A typical with 5 V supplies and 75 A typical with 3 V supplies. If a crystal or ceramic resonator is used as the clock source, the total current in standby mode is 400 A typical with 5 V supplies and 90 A with 3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system clock is provided by the AD7707's clock, so that the AD7707 produces an uninterrupted master clock even when it is in its standby mode. The serial interface remains operational when in standby mode so that data can be read from the output register in standby, regardless of whether or not the master clock is stopped.
The AD7707 operates with power supplies between 2.7 V and 5.25 V. There is no specific power supply sequence required for the AD7707, either the AVDD or the DVDD supply can come up first. In normal operation the DVDD must not exceed AVDD by 0.3 V. While the latch-up performance of the AD7707 is good, it is important that power is applied to the AD7707 before signals at REF IN, AIN or the logic input pins in order to avoid excessive currents. If this is not possible, the current that flows in any of these pins should be limited to less than 100 mA. If separate supplies are used for the AD7707 and the system digital circuitry, the AD7707 should be powered up first. If it is not possible to guarantee this, current limiting resistors should be placed in series with the logic inputs to again limit the current. Latch-up current is greater than 100 mA.
1600 1400 1200 1000 IDD - A 800 600 USING CRYSTAL OSCILLATOR TA = +25 C UNBUFFERED MODE GAIN = 128
fCLK = 2.4576MHz
fCLK = 1MHz
400 200 0 2.5
3.0
3.5
4.0 VDD
4.5
5.0
5.5
Figure 17. IDD vs. Supply Voltage
-26-
REV. A
AD7707
Supply Current
The current consumption on the AD7707 is specified for supplies in the range +2.7 V to +3.3 V and in the range +4.75 V to +5.25 V. The part operates over a +2.7 V to +5.25 V supply range and the IDD for the part varies as the supply voltage varies over this range. There is an internal current boost bit on the AD7707 that is set internally in accordance with the operating conditions. This affects the current drawn by the analog circuitry within these devices. Minimum power consumption is achieved when the AD7707 is operated with an fCLKIN of 1 MHz or at gains of 1 to 4 with fCLKIN = 2.4575 MHz as the internal boost bit is off reducing the analog current consumption. Figure 17 shows the variation of the typical IDD with VDD voltage for both a 1 MHz crystal oscillator and a 2.4576 MHz crystal oscillator at +25C. The AD7707 is operated in unbuffered mode. The relationship shows that the IDD is minimized by operating the part with lower VDD voltages. IDD on the AD7707 is also minimized by using an external master clock or by optimizing external components when using the on-chip oscillator circuit. Figures 3, 4, 6 and 7 show variations in IDD with gain, VDD and clock frequency using an external clock.
Grounding and Layout
side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. All analog supplies should be decoupled with 10 F tantalum in parallel with 0.1 F ceramic capacitors to GND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 F disc ceramic capacitors to DGND.
Evaluating the AD7707 Performance
The recommended layout for the AD7707 is outlined in the evaluation board. The evaluation board package include a fully assembled and tested evaluation board, documentation, software for controlling the board over the printer port of a PC and software for analyzing their performance on the PC. Noise levels in the signals applied to the AD7707 may also affect performance of the part. The AD7707 software evaluation package allows the user to evaluate the true performance of the part, independent of the analog input signal. The scheme involves using a test mode on the part where the inputs to the AD7707 are internally shorted together to provide a zero differential voltage for the analog modulator. External to the device, the LOCOM and HICOM inputs on the AD7707 should be connected to voltages that are within the allowable commonmode range of the part. This scheme should be used after a calibration has been performed on the part.
DIGITAL INTERFACE
Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator. As a result, the AD7707 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7707 is so high, and the noise levels from the AD7707 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7707 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place to avoid ground loops. If the AD7707 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point which should be established as close as possible to the AD7707. Avoid running digital lines under the device as these might couple noise onto the analog circuitry within the AD7707. The analog ground plane should be allowed to run under the AD7707 to reduce noise coupling. The power supply lines to the AD7707 should use wide traces to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component REV. A
As previously outlined, the AD7707's programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part's serial interface and read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the Communications Register. After power-on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any other register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The AD7707's serial interface consists of five signals, CS, SCLK, DIN, DOUT and DRDY. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the AD7707's data register. DRDY goes low when a new data word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7707 in systems where a number of parts are connected to the serial bus.
-27-
AD7707
Figures 18 and 19 show timing diagrams for interfacing to the AD7707 with CS used to decode the part. Figure 17 is for a read operation from the AD7707's output shift register while Figure 18 shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though the DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. The AD7707 serial interface can operate in three-wire mode by tying the CS input low. In this case, the SCLK, DIN and DOUT lines are used to communicate with the AD7707 and the status of DRDY can be obtained by interrogating the MSB of the Communications Register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. The AD7707 can also be operated with CS used as a frame synchronization signal. This scheme is suitable for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS since CS would normally occur after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers provided the timing numbers are obeyed. The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7707 DIN line for at least 32 serial clock cycles the serial interface is reset. This ensures that in three-wire systems, if the interface gets lost either via a software error or by some glitch in the system, it can be reset back to a known state. This state returns the interface to where the AD7707 is expecting a write operation to its Communications Register. This operation in itself does not reset the contents of any registers but since the interface was lost, the information written to any of the registers is unknown and it is advisable to set up all registers again. Some microprocessor or microcontroller serial interfaces have a single serial data line. In this case, it is possible to connect the AD7707's DATA OUT and DATA IN lines together and connect them to the single data line of the processor. A 10 k pullup resistor should be used on this single data line. In this case, if the interface gets lost, because the read and write operations share the same line the procedure to reset it back to a known state is somewhat different than previously described. It requires a read operation of 24 serial clocks followed by a write operation where a Logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back into a known state.
CONFIGURING THE AD7707
The AD7707 contains six on-chip registers that the user can accesses via the serial interface. Communication with any of these registers is initiated by writing to the Communications Register first. Figure 20 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7707. The flowchart also shows two different read options-- the first where the DRDY pin is polled to determine when an update of the data register has taken place, the second where the DRDY bit of the Communications Register is interrogated to see if a data register update has taken place. Also included in the flowing diagram is a series of words that should be written to the registers for a particular set of operating conditions. These conditions are gain of one, no filter sync, bipolar mode, buffer off, clock of 4.9512 MHz and an output rate of 50 Hz.
DRDY
t3
CS
t10
t4
SCLK
t6
t8
t5
DOUT MSB
t7
LSB
t9
Figure 18. Read Cycle Timing Diagram
CS
t11
SCLK
t14
t16
t12
DIN MSB
t13
t15
LSB
Figure 19. Write Cycle Timing Diagram
-28-
REV. A
AD7707
START
POWER-ON/RESET FOR AD7707
CONFIGURE & INITIALIZE C/ P SERIAL PORT
WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE CLOCK REGISTER (20 HEX)
WRITE TO CLOCK REGISTER SETTING THE CLOCK BITS IN ACCORDANCE WITH THE APPLIED MASTER CLOCK SIGNAL AND SELECT UPDATE RATE FOR SELECTED CHANNEL (0C HEX)
WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL & SETTING UP NEXT OPERATION TO BE A WRITE TO THE SETUP REGISTER (10 HEX)
WRITE TO SETUP REGISTER CLEARING F SYNC, SETTING UP GAIN, OPERATING CONDITIONS & INITIATING A SELF-CALIBRATION ON SELECTED CHANNEL (40 HEX)
POLL DRDY PIN
NO
DRDY LOW?
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE COMMUNICATIONS REGISTER (08 HEX)
YES WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) READ FROM COMMUNICATIONS REGISTER
POLL DRDY BIT OF COMMUNICATIONS REGISTER READ FROM DATA REGISTER
NO
DRDY LOW?
YES
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX)
READ FROM DATA REGISTER
Figure 20. Flowchart for Setting Up and Reading from the AD7707
REV. A
-29-
AD7707
MICROCOMPUTER/MICROPROCESSOR INTERFACING
VDD VDD SS
The AD7707's flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of Figure 20 outlines the sequence that should be followed when interfacing a microcontroller or microprocessor to the AD7707. Figures 21, 22 and 23 show some typical interface circuits. The serial interface on the AD7707 is capable of operating from just three wires and is compatible with SPI interface protocols. The three-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of optoisolators required in the system. The serial clock input is a Schmitt triggered input to accommodate slow edges from optocouplers. The rise and fall times of other digital inputs to the AD7707 should be no longer than 1 s. Most of the registers on the AD7707 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of microcontrollers. The Data Register on the AD7707 is 16 bits, and the offset and gain registers are 24-bit registers but data transfers to these registers can consist of multiple 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7707. Even though some of the registers on the AD7707 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the Setup Register is to be updated, the processor must first write to the Communications Register (saying that the next operation is a write to the Setup Register) and then write eight bits to the Setup Register. If required, this can all be done in a single 16-bit transfer because once the eight serial clocks of the write operation to the Communications Register have been completed, the part immediately sets itself up for a write operation to the Setup Register.
AD7707 to 68HC11 Interface
AD7707
RESET
68HC11
SCK
SCLK
MISO
DATA OUT
MOSI
DATA IN
CS
Figure 21. AD7707 to 68HC11 Interface
The 68HC11 is configured in the master mode with its CPOL bit set to a logic one and its CPHA bit set to a logic one. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7707 is not capable of full duplex operation. If the AD7707 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active. Similarly, if the AD7707 is configured for a read operation, data presented to the part on the DATA IN line is ignored even when SCLK is active. Coding for an interface between the 68HC11 and the AD7707 is given in Table XV. In this example, the DRDY output line of the AD7707 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status.
VDD
AD7707
RESET
8XC51
VDD
Figure 21 shows an interface between the AD7707 and the 68HC11 microcontroller. The diagram shows the minimum (three-wire) interface with CS on the AD7707 hard-wired low. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the DRDY output line from the AD7707. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 68HC11's port bits (such as PC0), which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt driven system, in which case the DRDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7707, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input.
P3.0
DATA OUT
DATA IN
P3.1
SCLK
CS
Figure 22. AD7707 to 8XC51 Interface
-30-
REV. A
AD7707
AD7707 to 8051 Interface AD7707 to ADSP-2103/ADSP-2105 Interface
An interface circuit between the AD7707 and the 8XC51 microcontroller is shown in Figure 22. The diagram shows the minimum number of interface connections with CS on the AD7707 hard-wired low. In the case of the 8XC51 interface the minimum number of interconnects is just two. In this scheme, the DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the DRDY output line from the AD7707. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 8XC51's port bits (such as P1.0) which is configured as an input. This port bit is then polled to determine the status of DRDY. The second scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7707, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the CS input. The 8XC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DATA OUT and DATA IN pins of the AD7707 should be connected together with a 10 k pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. The 8XC51 outputs the LSB first in a write operation, while the AD7707 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7707 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data read into the serial buffer needs to be rearranged before the correct data word from the AD7707 is available in the accumulator.
Figure 23 shows an interface between the AD7707 and the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the DRDY bit of the Communications Register is again monitored to determine when the Data Register is updated. The alternative scheme is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ADSP-2105. The serial interface of the ADSP2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7707 is active when either the RFS or TFS outputs from the ADSP-2103/ADSP-2105 are active. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7707.
CODE FOR SETTING UP THE AD7707
Table XVII gives a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7707. The sample program sets up the various registers on the AD7707 and reads 1000 samples from the part into the 68HC11. The setup conditions on the part are exactly the same as those outlined for the flowchart of Figure 20. In the example code given here, the DRDY output is polled to determine if a new valid word is available in the data register. The sequence of the events in this program are as follows: 1. Write to the Communications Register, selecting channel one as the active channel and setting the next operation to be a write to the clock register. 2. Write to Clock Register setting the CLK DIV bit which divides the external clock internally by two. This assumes that the external crystal is 4.9512 MHz. The update rate is selected to be 50 Hz. 3. Write to Communication Register selecting Channel 1 as the active channel and setting the next operation to be a write to the Setup Register. 4. Write to the Setup Register, setting the gain to 1, setting bipolar mode, buffer off, clearing the filter synchronization and initiating a self-calibration. 5. Poll the DRDY output. 6. Read the data from the Data Register. 7. Loop around doing Steps 5 and 6 until the specified number of samples have been taken from the selected channel.
ADSP-2103/ ADSP-2105
VDD
AD7707
RESET
RFS TFS DR
CS
DATA OUT
DT
DATA IN
SCLK
SCLK
Figure 23. AD7707 to ADSP-2103/ADSP-2105 Interface
REV. A
-31-
AD7707
Table XVIII. C Code for Interfacing AD7707 to 68HC11
/* This program has read and write routines for the 68HC11 to interface to the AD7707 and the sample program sets the various registers and then reads 1000 samples from one channel. */ #include #include #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main () { /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg (0x20); /* Active Channel is AIN1/LOCOM, next operation as write to the clock register */ Writetoreg (0x18); /* master clock enabled, 4.9512MHz Clock, set output rate to 50Hz*/ Writetoreg (0x10); /* Active Channel is AIN1/LOCOM, next operation as write to the setup register */ Writetoreg (0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/ while (PORTC and 0x10); /* wait for /DRDY to go low */ for (a=0;a-32-
REV. A
AD7707
APPLICATIONS
The AD7707 provides a low cost, high resolution analog-todigital function with two low level input channels and one high level input channel. Because the analog-to-digital function is provided by a sigma-delta architecture, it makes the part more immune to noisy environments thus making the part ideal for use in industrial and process control applications. It also provides a programmable gain amplifier, a digital filter and calibration options. Thus, it provides far more system level functionality than off-the-shelf integrating ADCs without the disadvantage of having to supply a high quality integrating capacitor. In addition, using the AD7707 in a system allows the system designer to achieve a much higher level of resolution because noise performance of the AD7707 is better than that of the integrating ADCs. The on-chip PGA allows the AD7707 to handle an analog input voltage ranges as low as 10 mV full-scale with VREF = +1.25 V. The pseudo-differential input capability of the low level channel allows this analog input range to have an absolute value anywhere between AGND - 100 mV and AVDD + 30 mV when the part is operated in unbuffered mode. It allows the user to connect the transducer directly to the input of the AD7707. In addition, the three-wire digital interface on the AD7707 allows data acquisition front ends to be isolated with just three wires. The AD7707 can be operated from a single 3 V or 5 V and its low power operation ensures that very little power needs to be brought across the isolation barrier in an isolated application.
Data Acquisition
signals up to 10 V in amplitude. This application shows the high level input channel being used to convert a number of input signals provided through an external mux controlled by the system microcontroller. Switching channels on the external multiplexer is equivalent to providing a step change on the AIN3 input. It takes 3 or 4 updates before the correct output code corresponding to the new analog input appears at the output. Therefore, when switching between channels on the external mux the first three outputs should be ignored following the channel change or the FSYNC bit in the setup register should be used to reset the digital filter and ensure that the DRDY is set high until a valid result is available in the output register.
Smart Valve/Actuator Control
Another area where the low power, single supply and high voltage input capability is of benefit is in smart valve and and actuator control circuits. The AD7707 monitors the signal from the control valve. The controller and the AD7707 form a closedloop control circuit. Figure 25 shows a block diagram of a smart actual or control circuit which includes the AD7707. The AD7707 monitors the valve position via a high quality servo pot whose output is 10 V. Similar applications for the AD7707 would be in the area of smart transmitters. Here, the entire smart transmitter must operate from the 4 mA to 20 mA loop. Tolerances in the loop mean that the amount of current available to power the transmitter is as low as 3.5 mA. The AD7707 consumes only 280 A, leaving at least 3 mA available for the rest of the transmitter. Figure 26 shows a block diagram of a smart transmitter which includes the AD7707.
Figure 24 shows a data acquisition system showing in which the low level input channel is used to digitize signals from a thermocouple and the high level input channel converts process control
+5V
+5V
CJC
AD590
AIN2 8.2k
AVDD
DVDD MCLK IN
THERMOCOUPLE JUNCTION +15V
AIN1 LOCOM MCLK OUT
AD7707
10V INPUT 0V TO 10V INPUT 5V INPUT 0V TO 5V INPUT 4-20mA 250 0-20mA 250 IN1 IN2 IN3 IN4 IN5 VDD OUT AIN3 REF IN(+) 2.5V VBIAS HICOM SCLK CS DIN DOUT
MICROCONTROLLER
SCLK PO DOUT DIN P1 P2 P3
ANALOG MULTIPLEXER
IN6 VSS A0 A1 A2
REF IN(-) AGND DGND
-15V
Figure 24. Data Acquisition System Using the AD7707
REV. A
-33-
AD7707
SMART VALVE/ACTUATOR +5V AVDD ACTUATOR/ VALVE 10V AIN2 DVDD MCLK IN
AD7707
AIN3 REF IN(+) 2.5V VBIAS HICOM REF IN(-) AGND DGND MICROCONTROLLER MCLK OUT
AD420 DAC CONTROL ROOM
AIN1 RSENSE LOCOM
Figure 25. Smart Valve/Actuator Control Using the AD7707
MAIN TRANSMITTER ASSEMBLY
3V 2.2 F 0.1 F DN25D
1.25V 4.7 F AVDD AVDD REF IN 100k VCC MICROCONTROLLER UNIT REF OUT2 SENSORS RTD mV THERMOCOUPLE V *PID *RANGE SETTING *CALIBRATION *LINEARIZATION *OUTPUT CONTROL *SERIAL COMMUNICATION *HART PROTOCOL COM REF IN 4.7 F VCC REF OUT1 BOOST COMP DRIVE 1000pF LOOP RTN COM 0.01 F 4mA TO 20mA 1k
AD7707
AIN1 AIN2 AIN3 MCLK OUT MCLK IN
AD421
C1 C2 C3
0.01 F AGND DGND
0.0033 F
0.01 F
Figure 26. Smart Transmitter Using the AD7707
-34-
REV. A
AD7707
Pressure Measurement Thermocouple Measurement
Other typical applications for the AD7707 include temperature and pressure measurement. Figure 27 shows the AD7707 used with a pressure transducer, the BP01 from Sensym. The pressure transducer is arranged in a bridge network and gives a differential output voltage between its OUT(+) and OUT(-) terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (i.e., the voltage between its IN(+) and IN(-) terminals). Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The low level input channels are ideal for this type of low signal measurement application. The excitation voltage for the bridge is also used to generate the reference voltage for the AD7707. Therefore, variations in the excitation voltage do not introduce errors in the system. Choosing resistor values of 24 k and 15 k, as per Figure 27, gives a 1.92 V reference voltage for the AD7707 when the excitation voltage is 5 V. Using the part with a programmed gain of 128 results in the full-scale input span of the AD7707 being 15 mV, which corresponds with the output span from the transducer.
+5V EXCITATION VOLTAGE = +5V IN(+) OUT(+) OUT(-) AIN1 LOCOM 24k AVDD DVDD MCLK IN
Another application area for the AD7707 is in temperature measurement. Figure 28 outlines a connection from a thermocouple to the AD7707. In this application, the AD7707 is operated in its unbuffered mode to accommodate signals of 100 mV on the front end. Cold conjunction compensation is implemented using the AD590 temperature transducer that produces an output current proportional to absolute temperature.
+5V +5V CJC THERMOCOUPLE JUNCTION
AD590
AVDD AIN2
DVDD MCLK IN
8.2k AIN1 LOCOM
+5V
AD7707
REF192
GND OUT REF IN(+) REF IN(-) DRDY SCLK AGND DGND DIN DOUT CS
MCLK OUT
CONTROLLER
Figure 28. Thermocouple Measurement Using the AD7707
IN(-)
AD7707
REF IN(+)
MCLK OUT
15k
REF IN(-) DRDY SCLK AGND DGND DIN DOUT CS CONTROLLER
Figure 27. Pressure Measurement Using the AD7707
REV. A
-35-
AD7707
RTD Measurement Chart Recorders
Figure 29 shows another temperature measurement application for the AD7707. In this case, the transducer is an RTD (Resistive Temperature Device), a PT100. The arrangement is a 4lead RTD configuration. There are voltage drops across the lead resistances RL1 and RL4 but these simply shift the commonmode voltage. There is no voltage drop across lead resistances RL2 and RL3 as the input current to the AD7707 is very low. The lead resistances present a small source impedance so it would not generally be necessary to turn on the buffer on the AD7707. If the buffer is required, the common-mode voltage should be set accordingly by inserting a small resistance between the bottom end of the RTD and GND of the AD7707. In the application shown, an external 400 A current source provides the excitation current for the PT100 and also generates the reference voltage for the AD7707 via the 6.25 k resistor. Variations in the excitation current do not affect the circuit as both the input voltage and the reference voltage vary radiometrically with the excitation current. However, the 6.25 k resistor must have a low temperature coefficient to avoid errors in the reference voltage over temperature.
+5V 400 A AVDD REF IN(+) REF IN(+) 6.25k REF IN(-) RL1 RL2 RTD REF IN(-) MCLK OUT DVDD MCLK IN
Another area where both high and low level input channels are usually found is in chart recorder applications. Circular chart recorders generally have two requirements. The first which would utilize the low level input channels of the AD7707 to measure inputs from thermocouples, RTDs and pressure sensors. The second requirement is to be able to measure dc input voltage ranges up to 10 V. The high level input channel is ideally suited to this measurement as there is no external signal conditioning required to accommodate these high level input signals.
AIN1
AD7707
RL3 LOCOM DRDY SCLK AGND DGND DIN DOUT CS CONTROLLER
RL4
Figure 29. RTD Measurement Using the AD7707
-36-
REV. A
AD7707
Accommodating Various High Level Input Ranges
The high level input channel, AIN3 can accommodate input signals from -11 V to +30 V on its input. This is achieved using on-chip thin film resistors that map the signal on AIN3 into a usable range for the AD7707. The input structure is arranged so that the sigma-delta converter sees the same impedance at its AIN(+) and AIN(-) inputs. The signal on the AIN3 input is referenced to the HICOM input and the VBIAS signal is used to adjust the common-mode voltage at the modulator input. In normal 5 V operation VBIAS is normally connected to 2.5 V and HICOM is connected to AGND. This arrangement ensures that the voltages seen at the modulator input are within the common-mode range of the buffer. The differential voltage, AIN, seen by the AD7707 when using the high level input channel is the difference between AIN3(+) and AIN3(-) as shown in Figure 30 and must remain within the absolute common-mode range of the modulator. AIN3(+) = (AIN3 + 6 x VBIAS+ V (HICOM))/8 AIN3(-) = 0.75 x VBIAS + 0.25 V (HICOM) AIN = (AIN3 - V (HICOM))/8
30k AIN3 5k VBIAS 5k AIN AIN3(+) MUX AIN3(-) 15k HICOM 30k
Figure 30. AIN3, High Level Input Channel Structure
The VBIAS and HICOM inputs are used to tailor the input range on the high level input channel to suit a variety of input ranges. The following table applies for operation with AVDD = 5 V, and REF(+) - REF(-) = 2.5 V.
Table XIX
AIN3 RANGE 10 V 5 V 0 V to 10 V 0 V to 20 V -5 V to +10 V
VBIAS 2.5 V 2.5 V 2.5 V AGND 2.5 V 2.5 V
HICOM AGND AGND AGND AGND AGND 2.5 V
GAIN 2 4 2 1 1 2
BUF/UNBUF BUF/UNBUF BUF/UNBUF BUF/UNBUF UNBUF UNBUF BUF/UNBUF
AIN RANGE 1.875 V 1.25 V 1.875 V 0.625 V 1.875 V to 3.125 V 0 V to 2.5 V 1.875 V to 4.375 V 2.5 V 0.9375 V
The following table applies for operation with AVDD = 3 V, and REF(+) - REF(-) = 1.25 V.
Table XX
AIN3 RANGE 5 V 0 V to 10 V -5 V to +10 V -7.5 V to +10 V 10 V
Typical Input Currents
VBIAS 1.25 V 1.25 V 1.25 V 1.25 V 1.666 V
HICOM AGND AGND 2.5 V 0 AGND
GAIN 2 1 1 1 1
BUF/UNBUF UNBUF UNBUF UNBUF UNBUF UNBUF
AIN RANGE 0.9375 V 0.625 V 0.9375 V to 2.1875 V 1.5625 V 0.9375 V 0 V to 2.1875 V 1.25 V 1.25 V
When using the high level input channel, power dissipation is determined by the currents flowing in the AIN3, VBIAS and HICOM inputs. The voltage level applied to these inputs determines whether the external source driving these inputs needs to sink of source current. The following table shows the currents associated with the 10 V input range. These inputs should be driven from a low impedance source in all applications to prevent significant gain errors being introduced.
Table XXI
AIN3 -10 V 0V +10 V
VBIAS 2.5 V 2.5 V 2.5 V
HICOM AGND AGND AGND
I (AIN3) -354 A -62 A 229 A
I (VBIAS) 500 A 250 A 0
I (HICOM) -146 A -188 A -229 A
REV. A
-37-
AD7707
APPENDIX 1. OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 (5 V OPERATION)
Specified high level input voltage ranges of 10 V, 5 V, 0 V to +10 V and 0 V to +5 V only utilize two gain different gain settings (gains of 2 and 4) out of the eight possible settings available within the PGA. The tables here show what the high level channel performance actually is over the complete range of gain settings. Table XXII shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers are given for all input ranges with a VREF of +2.5 V, HBIAS = 2.5 V, HICOM = AGND and AVDD = 5 V. These numbers are typical and are generated at an analog input voltage of 0 V for buffered mode of operation. Table XXIII meanwhile shows the rms and peak-to-peak resolution for buffered mode of operation. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
Table XXII. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V Unbuffered Mode
Filter First Notch and O/P Data Rate
-3 dB Gain of Frequency 1 10.90 (16) 31.34 (16) 36.74 (16) 690 (13) 4679 (10)
Typical Output RMS Noise in V (Peak-to-Peak Resolution) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 5.10 (16) 15.82 (16) 20.36 (16) 430 (13) 2350 (10) 3.52 (16) 9.77 (16) 12.29 (16) 212 (13) 1287 (10) 2.62 (16) 6.00 (16) 7.33 (16) 100 (13) 564 (10) 2.34 (16) 5.12 (16) 5.84 (16) 42 (13) 294 (10) 2.34 (16) 5.36 (15) 5.65 (15) 30 (13) 137 (10) 2.34 (15) 4.84 (14) 5.1 (14) 18.5 (12) 73 (10)
Gain of 128 2.30 (14) 4.75 (13) 5.3 (13) 13.8 (12) 53 (10)
MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz
Table XXIII. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V Buffered Mode Filter First Notch and O/P Data Rate Typical Output RMS Noise in V (Peak-to-Peak Resolution) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64
-3 dB Gain of Frequency 1
Gain of 128
MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz
14.28 (16) 37.4 (16) 48.8 (16) 778 (12.5) 4716 (10.5)
7.4 (16) 22.2 (16) 26.6 (16) 475 (13) 2423 (10.5)
5.2 (16) 14.3 (16) 15.88 (16) 187 (13) 1097 (10.5)
3.35 (16) 8.7 (16) 10.17 (16) 98 (13) 551 (10.5)
3.35 (16) 7.33 (15.5) 8.78 (15.5) 60 (12.5) 288 (10.5)
3.34 (15.5) 7.7 (14.5) 8.1 (14.5) 31.7 (12.5) 150 (10)
3.34 (15) 7.6 (13.5) 8.1 (13.5) 23 (12) 81 (10)
2.34 (14.5) 7.5 (12.5) 8.1 (12.5) 18.3 (11.5) 49 (10)
Output Noise For High Level Input Channel, AIN3 (3 V Operation)
Table XXIV shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and -3 dB frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers are given for all input ranges with a VREF of +1.25 V, HBIAS = 1.25 V, HICOM = AGND and AVDD = 3 V. These numbers are typical and are generated at an analog input voltage of 0 V for unbuffered mode of operation. Table XXV meanwhile shows the output rms noise and peak-topeak resolution for buffered mode of operation with the same operating conditions as above. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of resolution.
-38-
REV. A
AD7707
Table XXIV. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V Unbuffered Mode
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz 12.4 (16) 30.35 (16) 34.55 (16) 498 (13) 2266 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 7.02 (16) 16.4 (16) 19.13 (16) 204 (13) 1151 (10.5) 3.87 (16) 9.4 (16) 10.9 (16) 105 (13) 554 (10.5) 2.41 (16) 5.85 (16) 6 (16) 57.5 (13) 280 (10.5) 2.39 (16) 5.2 (15) 5.8 (15) 27.5 (13) 136 (10.5) 2.3 (15.5) 4.5 (14.5) 5.62 (14) 17.4 (12.5) 83 (10) 2.29 (14.5) 4.5 (13.5) 5.2 (13) 12.7 (12) 39 (10)
Gain of 128 2.13 (13.5) 5.09 (12) 6.14 (12) 11.42 (11) 27.5 (9.5)
Table XXV. AIN3, Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V Buffered Mode
Filter First Notch and O/P -3 dB Gain of Data Rate Frequency 1 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 50 Hz 13.1 Hz 60 Hz 15.72 Hz 250 Hz 65.5 Hz 500 Hz 131 Hz 14.84 (16) 36.1 (16) 38.8 (16) 420 (13) 2234 (10.5)
Typical Output RMS Noise in V (Peak-to-Peak Resolution) Gain of Gain of Gain of Gain of Gain of Gain of 2 4 8 16 32 64 8.39 (16) 18.8 (16) 21.55 (16) 194 (13) 1231 (10.5) 5.56 (16) 11.5 (16) 13.39 (16) 97.6 (13) 534 (10.5) 3.45 (16) 7.5 (15.5) 8.5 (15.5) 54.5 (12.5) 275 (10.5) 3.3 (16) 7.4 (14.5) 8.36 (14.5) 30 (12.5) 145 (10.5) 3.2 (15) 7.43 (13.5) 8 (13.5) 22 (12) 71 (10.5) 3.2 (14) 6.8 (12.5) 8.2 (12.5) 18 (11.5) 48 (10)
Gain of 128 3.3 (13) 7 (12) 7.7 (12) 16.7 (10.5) 31 (9.5)
REV. A
-39-
AD7707
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead SOIC (R-20)
0.5118 (13.00) 0.4961 (12.60)
20
11
0.2992 (7.60) 0.2914 (7.40)
1 10
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-40-
REV. A
PRINTED IN U.S.A.
C3580a-2.5-2/00 (rev. A)

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